1. Field of the Invention
The present invention relates to an element isolation technique suitably applicable to the production of various semiconductor devices.
2. Prior Art
With a trend to miniaturization and speedup of various electronic appliances, various production-related techniques have been developed with a view to attaining higher-density integration of semiconductor devices (hereinafter often referred to simply as "devices") constituting electronic appliances as mentioned above.
As one of the above-mentioned conventional production-related techniques, there is known a technique of forming an isolation region(s) on a substrate, which include a widely-used selective oxidation (LOCOS: local oxidation of silicon) method in which only the isolation region(s) of a silicon substrate is selectively oxidized using silicon nitride (Si.sub.X N.sub.Y, wherein X and Y are each a positive number) as an oxidation-resistant mask. Additionally stated, in the following description, an "isolation region" as a constituent part is distinguished in usage of term from a "field region" as a kind of site of a substrate predetermined in accordance with the designing there of.
As is well known, so-called bird's breaks sometimes appear in the case of the LOCOS method. This entails an increase in the area of a field region in comparison with the area of an active region based on the designing of a device, according to an isolation technique using the LOCOS method.
Further, in the LOCOS method, decreases in the sizes of the field region and the active region or a decrease in the size of any one of the above-mentioned two regions brings about various disadvantages such as a narrow channel effect of increasing the threshold value V.sub.T of a transistor and a poor threshold value of an inactive transistor.
Thus, the fact is that the LOCOS method cannot cope with the miniaturization and high-density integration of devices.
A known isolation technique alternative to the LOCOS method is disclosed in, for example, Literature I: "1984 Symposium on VLSI Technology," pp. 28-29, 1984. This technique is called a "trench isolation method."
An example of the above-mentioned conventional trench isolation method will now be described while referring to the accompanying drawings.
FIGS. 1(a) to 1(h) are schematic cross-sectional views of structures produced in major steps of a process, which are illustrative of a conventional technique using the trench isolation method.
First, a pad oxide film 13 made of silicon oxide (SiO.sub.Z wherein Z is a positive number) and having a thickness of about 400 .ANG. is formed on the upper surface of a substrate 11 by, for example, a chemical vapor deposition (CVD) method or a thermal oxidation treatment. Thereafter, an oxidation-resistant film 15, made of silicon nitride (Si.sub.X N.sub.Y) and having a thickness of about 1,600 .ANG., and a mask film 17 for use in formation of a trench, made of silicon oxide (SiO.sub.Z) and having a thickness of about 2,000 .ANG., are sequentially deposited on the pad oxide film 13 by, for example, a CVD method to obtain a structure as shown in FIG. 1(a).
Subsequently, a resist pattern (not shown in the figures) is provided on the upper surface areas of the above-mentioned structure corresponding to active regions 19 of the substrate 11. Thereafter, the mask film 17 for use in the formation of the trench, the oxidation-resistant film 15 and the pad oxide film 13 are sequentially removed only from an area thereof located on a field region 21 of the substrate 11 by etching with the resist pattern serving as an etching mask according to an anisotropic etching technique such as a reactive ion etching (RIE) method.
According to the foregoing procedure, an opening 23, partially exposing the upper surface of the substrate 11 and having side face extending vertically along the above-mentioned three layers 13, 15 and 17 up to the level of the upper surface of the substrate 11, is formed as shown in FIG. 1(b).
Subsequently, a trench 29, having a side face 25 perpendicular to the upper surface of the substrate 11 and a bottom face 27 parallel therewith, is formed by the above-mentioned RIE method while utilizing as an etching mask the three layers 13, 15 and 17 remaining on the active regions 19.
Thereafter, the above-mentioned three layers 13, 15 and 17 remaining on the active regions 19 are used as a mask for ion implantation to effect the ion implantation (indicated by a range of arrows a in FIG. 1(c) of a p-type impurity such as boron ions (B.sup.+) through the above-mentioned trench 29 to thereby form a channel stop region 31 as shown in FIG. 1(c).
Subsequently, the resulting structure having the formed trench 29 is subjected to a thermal oxidation treatment to form an inner surface oxide film 33 as shown in FIG. 1(d) in an inner surface portion along the side face 25 and the bottom face 27 of the above-mentioned trench 29.
Subsequently, a polycrystalline silicon (poly-Si) film 35 is deposited on the whole upper surface of the structure as shown in FIG. 1(d). The deposition of the poly-Si film 35 is done to such an extent as to fill up the aforementioned trench 29 and the opening 23 with the poly-Si film 35 as well as cover the upper surface of the above-mentioned structure with the poly-Si film 35. Thus, a structure as shown in FIG. 1(e) is obtained.
Subsequently, the above-mentioned poly-Si film 35 is etched to form a substantially planar surface 37 while leaving part of the poly-Si film 35 still at least completely filling therewith the above-mentioned trench 29 (see FIG. 1(f)).
The formation of the substantially planar surface 37 can be effected through an etching back treatment using one of various dry etching techniques or a wet etching technique wherein a hydrofluoric acid type etchant is used.
Thereafter, the mask film 17 for use in the formation of the trench which constitutes part of the surface portion of the structure at this stage is removed by etching. As a result, the poly-Si film 35 (having the substantially planar surface 37) remains on the field region 21, while the oxidation-resistant films 15 on the active regions 19 are exposed. The resulting structure is subjected to a thermal oxidation treatment to oxidize a top portion of the poly-Si film 35 to thereby form a top oxide film 39 having a thickness of about 3,000 .ANG. as shown in FIG. 1(g). This top oxide film 39 is integrated with the pad oxide film 13 and the inner surface oxide film 33.
Subsequently, the above-mentioned oxidation-resistant film 15 and the pad oxide film 13 are sequentially removed by etching to expose the upper surface of the substrate 11 in the active regions 19 while forming an isolation region 41 constituted of the remaining oxide film 39 and poly-Si film 35 in the field region 21 (see FIG. 1(h)).
As will be understandable from the foregoing description, the isolation region 41 is formed through the thermal oxidation treatments after the formation of the channel stop region 31. Even if the channel stop region 31 expands laterally (in a direction parallel with the upper surface of the substrate) as well as in the depth-wise direction of the substrate because of diffusion of implanted ions caused by the latter one of the above-mentioned thermal oxidation treatments, the adverse effect of the expansion of the channel stop region 31 on the source/drain regions of a device can be avoided because the channel stop region 31 is formed considerably apart from the source/drain regions, etc. Such a construction of a trench type isolation region(s) is effective in decreasing the widths of active regions in step with the higher-density integration of devices to be able to cope with a decrease in the dielectric strength due to the punch through effect, an increase in the narrow channel effect, etc.
Further, according to the foregoing technique, a volume expansion accompanies the growth of the oxide films from silicon because the isolation region 41 is formed through the thermal oxidation treatment of the poly-Si films 35. This volume expansion creates some stress, for example, in portions corresponding to the corners of the trench 29 to expand the above-mentioned portions in directions parallel with the upper surface of the substrate 11. The above-mentioned stress works to develop crystal defects in the proximity of the above-mentioned corners. Such crystal defects sometimes cause occurrence of electric current leaks in various types of devices, deterioration of the dielectric strength of gate oxide film, etc.
As one conventional method for mitigating the development of such crystal defects, there is a method wherein an isotropic etching treatment to form an undercut is effected before an anisotropic etching treatment in preparation for the formation of a trench as shown in FIGS. 1(b) and 1(c). According to this method, a trench (not shown in the figures) having an inner face obtusely angled with the upper surface of a substrate is formed to decrease the influence of the stress caused by the aforementioned growth of oxide films to thereby mitigate the development of crystal defects.
Further, crystal defects as mentioned above are also developed during the formation of the inner surface oxide film 33 as illustrated by reference to FIG. 1(d). As a countermeasure against this, the once-formed inner surface oxide film is removed by etching to eliminate the stress, followed by forming an inner surface oxide film again, whereby the development of crystal defects is mitigated.
The above-mentioned two types of treatments for the purpose of obviating the development of crystal defects (hereinafter referred to as "rounding treatments") can mitigate the occurrence of electric current leaks, the deterioration of the dielectric strength of gate oxide films, etc.
However, the foregoing conventional method of forming an embedded isolation region involves the following various problems.
(1) Where isolation regions with different widths or portions of an isolation region with different widths are required to be simultaneously formed on one substrate according to the design of a semiconductor device, a narrow trench or a narrow portion of a trench, and a wide trench or a wide portion of a trench are easy and hard, respectively, of being filled up with poly-Si in the step of filling the trench(es) with poly-Si. Therefore, it is difficult to control the thicknesses of poly-Si films or portions of a poly-Si film with which the trenches with the different widths or the portions of the trench with the different widths are to be simultaneously filled up. In such a case, even if a sufficiently thick poly-Si film(s) is deposited and etched back, the thickness of the poly-Si films or the portions of the poly-Si film embedded in the trench(es) are not equal with each other. Thus, simultaneous formation of element isolation regions with different widths or portions of an isolation portion with different widths on one substrate involves a problem of forming a complex uneven surface of the resulting structure.
(2) Where the aforementioned rounding treatment is effected for the purpose of mitigating the development of crystal defects caused by oxide film growth, there arises a problem that the yield may lower to the accompaniment of an increase in the number of steps.
(3) The aforementioned isolation region is formed by thermal oxidation of a poly-Si film embedded in a trench. When the trench is formed so as to have a sufficient depth, poly-Si remains on the inside of the isolation region. Therefore, the poly-Si film 15 surrounded by the inner oxide film 33 and the top oxide film 39 (see FIGS. 1(g) and 1(h)) is left in a floating state to present a problem that the resulting semiconductor device is in electrically unstable condition.
(4) The aforementioned isolation region is obtained in a state of the top oxide film 39 thereof being exposed to the outside of the substrate 11. In general, silicon oxide constituting the top oxide film 39 and silicon constituting the substrate 11 have mutual selectivities in respective etching treatments. This entails a problem of forming a different in level between the upper surface of the isolation region and the upper surfaces of the substrate corresponding to element regions.
In view of the foregoing various problems, an object of the present invention is to provide a process for forming an embedded isolation region(s) which can realize simplification of the process, higher-density integration of a device, an improvement in the reliability of the device, etc.